View GDPXA255_883826.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel? pxa255 processor electrical, mechanical, and thermal specification data sheet product features high performance processor ? intel? xscale? microarchitecture ?32 kb instruction cache ?32 kb data cache ?2 kb ?mini? data cache ?extensive data buffering intel? media processing technology ?enhanced 16-bit multiply ?40-bit accumulator flexible clocking ?cpu clock from 100 to 400 mhz ?flexible memory clock ratios ?frequency change modes rich serial peripheral set ?ac97 audio port ?i 2 s audio port ? usb client controller ?high speed uart ?second uart with flow control ?uart with hardware flow control ?fir and sir infrared comm ports low power ?less than 500 mw typical internal dissipation ?supply voltage may be reduced to 1.00 v ?low power/sleep modes high performance memory controller ?four banks of sdram - up to 100 mhz ?five static chip selects ?support for pcmcia or compact flash ? companion chip interface additional peripherals for system connectivity ?multimedia card controller (mmc) ?ssp controller ?network ssp controller for baseband ?i2c controller ?two pulse width modulators (pwms) ?all peripheral pins double as gpios hardware debug features hardware performance monitoring features order number: 278805-002 february, 2004
2 data sheet information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assu mes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel product s including liability or warranties relating to fitness for a particular purpose, merchantability, or infringeme nt of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pxa255 processor emts data sheet may contain design defects or errors known as errata which may cause the product to deviat e from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2004 *other names and brands may be claimed as the property of others.
pxa255 processor ? electrical, mechanical, and thermal specification data sheet 3 contents 1.0 about this document ............................................................................................ 7 2.0 functional overview ..............................................................................................7 3.0 package information ..............................................................................................8 3.1 package introduction..................................................................................... 8 3.1.1 functional signal definitions ............................................................8 3.1.1.1 pxa255 processor signal pin descriptions .....................8 3.2 package power ratings ..............................................................................22 4.0 electrical specifications ...................................................................................... 22 4.1 absolute maximum ratings......................................................................... 22 4.2 power consumption specifications ............................................................. 23 4.3 operating conditions................................................................................... 25 4.4 targeted dc specifications......................................................................... 26 4.5 targeted ac specifications ......................................................................... 27 4.6 oscillator electrical specifications............................................................... 28 4.6.1 32.768-khz oscillator specifications .............................................. 28 4.6.2 3.6864 mhz oscillator specifications .............................................29 4.7 reset and power ac timing specifications ................................................30 4.7.1 power-on timing ...........................................................................30 4.7.2 hardware reset timing.................................................................. 32 4.7.3 watchdog reset timing .................................................................32 4.7.4 gpio reset timing ........................................................................32 4.7.5 sleep mode timing ........................................................................33 4.8 memory bus and pcmcia ac specifications .............................................35 4.9 peripheral module ac specifications ..........................................................37 4.9.1 lcd module ac timing.................................................................. 37 4.9.2 ssp module ac timing.................................................................. 37 4.9.3 boundary scan test signal timings .............................................. 38 4.10 ac test conditions .....................................................................................39
pxa255 processor ? electrical, mechanical, and thermal specification 4 data sheet figures 1 processor block diagram...................................................................................... 8 2 pxa255 processor .............................................................................................. 19 3 power-on reset timing ...................................................................................... 31 4 hardware reset timing ...................................................................................... 32 5 gpio reset timing ............................................................................................. 33 6 sleep mode timing ............................................................................................. 34 7 lcd ac timing definitions ................................................................................. 37 8 ssp ac timing definitions ................................................................................. 38 9 ac test load ...................................................................................................... 39 tables 1 related documentation......................................................................................... 7 2 processor pin types ............................................................................................. 9 3 pin and signal descriptions for the pxa255 processor........................................ 9 4 pin description notes.......................................................................................... 18 5 pxa255 processor 256-lead 17x17mm mbga pinout ? ballpad no. order .... 20 6 ja and maximum power ratings........................................................................ 22 7 absolute maximum ratings ................................................................................ 23 8 power consumption specifications for pxa255 processor ................................ 24 9 voltage, temperature, and frequency electrical specifications......................... 25 10 standard input, output, and i/o pin dc operating conditions ........................... 26 11 standard input, output, i/o pin dc operating conditions for 2.5-v memory ..... 27 12 standard input, output, and i/o pin ac operating conditions ........................... 28 13 32.768-khz oscillator specifications................................................................... 28 14 3.6864-mhz oscillator specifications ................................................................. 29 15 power-on timing specifications ......................................................................... 31 16 hardware reset timing specifications ............................................................... 32 17 gpio reset timing specifications ...................................................................... 33 18 sleep mode timing specifications ...................................................................... 34 19 sram / rom / flash / synchronous fast flash ac specifications.................... 35 20 variable latency i/o interface ac specifications ............................................... 35 21 card interface (pcmcia or compact flash) ac specifications ......................... 36 22 synchronous memory interface ac specifications 1 .......................................... 36 23 lcd ac timing specifications ............................................................................ 37 24 ssp ac timing specifications ............................................................................ 38 25 boundary scan test signal timing ..................................................................... 38
pxa255 processor ? electrical, mechanical, and thermal specification data sheet 5 revision history date revision description march 2003 -001 first public release of the emts february 2004 -002 updated 400 mhz idle mode power.
pxa255 processor ? electrical, mechanical, and thermal specification 6 data sheet
about this document intel? pxa255 processor electrical, mechanical, and thermal specification 7 1.0 about this document this is the electrical, mechanical, and thermal specification data sheet for the intel? pxa255 processor. this data sheet contains a functional overview, mechanical data, package signal locations, targeted electrical specifications (simulated), and bus functional waveforms. detailed functional descriptions other than parametric performance is published in the intel? pxa255 processor developer's manual . refer to table 1, ?related documentation? for a list of documents that support the pxa255 processor. 2.0 functional overview the pxa255 processor provides high integration, high performance and low power consumption for portable handheld and handset devices. these processors incorporate the intel? xscale ? microarchitecture based on the arm* v5te architecture. refer to the intel? xscale ? microarchitecture for the intel? pxa250 and pxa 210 applications processors user?s manual for implementation details, extensions, and options implemented by the xscale microarchitecture. the processor memory interface supports a variety of memory types that allow flexible design requirements. hooks for connection to two companion chips permit glueless connection to external devices. an integrated lcd display controller supports displays and permits 1, 2, and 4-bit grayscale, and 8- or 16-bit color pixels. a 256-byte palette ram provides flexible color mapping capabilities. a rich set of serial devices as well as general-system resources provide enough compute and connectivity capability for many applications. for details on the programming model and theory of operation of each of these units, refer to the intel? pxa255 processor developer's manual . for the processor block diagram, refer to figure 1, ?processor block diagram? on page 8 . table 1. related documentation document title order / contact intel? pxa255 processor developer's manual 278693 intel? xscale tm microarchitecture for the pxa250 and pxa210 applications processors developer's manual 278525 intel? pxa255 processor design guide 278694
package information 8 intel? pxa255 processor electrical, mechanical, and thermal specification 3.0 package information 3.1 package introduction the pxa255 processor is offered in a 256-pin mbga (refer to figure 2, ?pxa255 processor? on page 19 ). 3.1.1 functional signal definitions 3.1.1.1 pxa255 processor signal pin descriptions table 3, ?pin and signal descriptions for the pxa255 processor? on page 9 describes the signal definitions for the pxa255 processor. figure 2, ?pxa255 processor? on page 19 illustrates the physical characteristics of the pxa255 processor. table 5, ?pxa255 processor 256-lead 17x17mm mbga pinout ? ballpad no. order? on page 20 describes the pinout for the pxa255 processor. figure 1. processor block diagram intel?xscale microarchitecture color or grayscale lcd controller rtc os timer pwm(2) int. controller clocks & power man. i 2 s ac97 uarts nssp slow irda ssp usb client general purpose i/o asic socket 0 socket 1 3.6864 mhz osc 32.768 khz osc dma controller and bridge xcvr sdram/ smrom 4 banks rom/ flash/ sram 4 banks i 2 c fast irda mmc peripheral bus system bus memory controller variable latency i/o control pcmcia & cf control dynamic memory control static memory control
package information intel? pxa255 processor electrical, mechanical, and thermal specification 9 some of the processor pins can be connected to multiple signals. the gafrn_m registers determine the signal connected to the pin. some signals can go to multiple pins. the signal must be routed to one pin only by using the gafrn_m registers. because this is true, some pins are listed twice?once in each unit that can use the pin. not all peripherals can be used simutaneously in one design because different peripherals share the same pins. table 2. processor pin types type function ic cmos input oc cmos output ocz cmos output, hi-z icocz cmos bidirectional, hi-z ia analog input oa analog output iaoa analog bidirectional sup supply pin (either vcc or vss) table 3. pin and signal descriptions for the pxa255 processor (sheet 1 of 9) pin name type signal descriptions reset state sleep state memory controller pins ma[25:0] ocz memory address bus. (output) signals the address requested for memory accesses. driven low driven low md[15:0] icocz memory data bus. (input/output) lower 16 bits of the data bus. hi-z driven low md[31:16] icocz memory data bus. (input/output) used for 32-bit memories. hi-z driven low noe ocz memory output enable. (output) connect to the output enables of memory devices to control data bus drivers. driven high note [4] nwe ocz memory write enable. (output) connect to the write enables of memory devices. driven high note [4] nsdcs[3:0] ocz sdram cs for banks 3 through 0. (output) connect to the chip select (cs) pins for sdram. for the pxa255 processor processor nsdcs0 can be hi-z, nsdcs1-3 cannot. driven high note [5] dqm[3:0] ocz sdram dqm for data bytes 3 through 0. (output) connect to the data output mask enables (dqm) for sdram. driven low driven low nsdras ocz sdram ras. (output) connect to the row address strobe (ras) pins for all banks of sdram. driven high driven high nsdcas ocz sdram cas. (output) connect to the column address strobe (cas) pins for all banks of sdram. driven high driven high sdcke[0] oc synchronous static memory clock enable. (output) connect to the cke pins of smrom. the memory controller provides control register bits for de-assertion. driven low driven low
package information 10 intel? pxa255 processor electrical, mechanical, and thermal specification sdcke[1] oc sdram and/or synchronous static memory clock enable. (output) connect to the clock enable pins of sdram. it is deasserted during sleep. sdcke[1] is always de-asserted upon reset. the memory controller provides control register bits for de-assertion. driven low driven low sdclk[0] oc synchronous static memory clock. (output) connect to the clock (clk) pins of smrom. it is driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. at reset, all clock pins are free running at the divide-by-2 clock speed and may be turned off via free-running control register bits in the memory controller. the memory controller also provides control register bits for clock division and deassertion of each sdclk pin. sdclk[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for smrom. sdclk[1] ocz sdram clocks (output) connect sdclk[1] and sdclk[2] to the clock pins of sdram in bank pairs 0/1 and 2/3, respectively. they are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. at reset, all clock pins are free running at the divide-by-2 clock speed and may be turned off via free-running control register bits in the memory controller. the memory controller also provides control register bits for clock division and de-assertion of each sdclk pin. sdclk[2:1] control register assertion bits are always de-asserted upon reset. driven low driven low sdclk[2] oc driven low driven low ncs[5]/ gpio[33] icocz static chip selects. (output) chip selects to static memory devices such as rom and flash. individually programmable in the memory configuration registers. ncs[5:0] can be used with variable latency i/o devices. pulled high - note[1] note [4] ncs[4]/ gpio[80] icocz ncs[3]/ gpio[79] icocz ncs[2]/ gpio[78] icocz ncs[1]/ gpio[15] icocz ncs[0] icocz static chip select 0. (output) chip select for the boot memory. ncs[0] is a dedicated pin. driven high note [4] rd/nwr ocz read/write for static interface. (output) signals that the current transaction is a read or write. driven low holds last state rdy/ gpio[18] icocz variable latency i/o ready pin. (input) notifies the memory controller when an external bus device is ready to transfer data. pulled high - note[1] note [3] l_dd[8]/ gpio[66] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller alternate bus master request. (input) allows an external device to request the system bus from the memory controller. pulled high - note[1] note [3] table 3. pin and signal descriptions for the pxa255 processor (sheet 2 of 9) pin name type signal descriptions reset state sleep state
package information intel? pxa255 processor electrical, mechanical, and thermal specification 11 l_dd[15]/ gpio[73] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller grant. (output) notifies an external device that it has been granted the system bus. pulled high - note[1] note [3] mbgnt/ gp[13] icocz memory controller grant. (output) notifies an external device that it has been granted the system bus. pulled high - note[1] note [3] mbreq/ gp[14] icocz memory controller alternate bus master request. (input) allows an external device to request the system bus from the memory controller. pulled high - note[1] note [3] pcmcia/cf control pins npoe/ gpio[48] icocz pcmcia output enable. (output) reads from pcmcia memory and to pcmcia attribute space. pulled high - note[1] note [5] npwe/ gpio[49] icocz pcmcia write enable. (output) performs writes to pcmcia memory and to pcmcia attribute space. also used as the write enable signal for variable latency i/o. pulled high - note[1] note [5] npiow/ gpio[51] icocz pcmcia i/o write. (output) performs write transactions to pcmcia i/o space. pulled high - note[1] note [5] npior/ gpio[50] icocz pcmcia i/o read. (output) performs read transactions from pcmcia i/o space. pulled high - note[1] note [5] npce[2]/ gpio[53] icocz pcmcia card enable 2. (output) selects a pcmcia card. npce[2] enables the high byte lane and npce[1] enables the low byte lane. mmc clock. (output) clock signal for the mmc controller. pulled high - note[1] note [5] npce[1]/ gpio[52] icocz pcmcia card enable 1. (outputs) selects a pcmcia card. npce[2] enables the high byte lane and npce[1] enables the low byte lane. pulled high - note[1] note [5] niois16/ gpio[57] icocz io select 16 . (input) acknowledge from the pcmcia card that the current address is a valid 16 bit wide i/o address. pulled high - note[1] note [5] npwait/ gpio[56] icocz pcmcia wait. (input) driven low by the pcmcia card to extend the length of the transfers to/from the pxa255 processor processor. pulled high - note[1] note [5] psktsel/ gpio[54] icocz pcmcia socket select. (output) used by external steering logic to route control, address, and data signals to one of the two pcmcia sockets. when psktsel is low, socket zero is selected. when psktsel is high, socket one is selected. has the same timing as the address bus. pulled high - note[1] note [5] npreg/ gpio[55] icocz pcmcia register select. (output) indicates that the target address on a memory transaction is attribute space. has the same timing as the address bus. pulled high - note[1] note [5] lcd controller pins l_dd(7:0)/ gpio[65:58] icocz lcd display data. (outputs) transfers pixel information from the lcd controller to the external lcd panel. pulled high - note[1] note [3] l_dd[8]/ gpio[66] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller alternate bus master request. (input) allows an external device to request the system bus from the memory controller. pulled high - note[1] note [3] table 3. pin and signal descriptions for the pxa255 processor (sheet 3 of 9) pin name type signal descriptions reset state sleep state
package information 12 intel? pxa255 processor electrical, mechanical, and thermal specification l_dd[9]/ gpio[67] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 0. (output) chip select 0 for the mmc controller. pulled high - note[1] note [3] l_dd[10]/ gpio[68] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 1. (output) chip select 1 for the mmc controller. pulled high - note[1] note [3] l_dd[11]/ gpio[69] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc clock. (output) clock for the mmc controller. pulled high - note[1] note [3] l_dd[12]/ gpio[70] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. rtc clock. (output) real-time clock 1 hz tick. pulled high - note[1] note [3] l_dd[13]/ gpio[71] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. 3.6864 mhz clock. (output) output from 3.6864 mhz oscillator. pulled high - note[1] note [3] l_dd[14]/ gpio[72] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. 32 khz clock. (output) output from the 32 khz oscillator. pulled high - note[1] note [3] l_dd[15]/ gpio[73] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. memory controller grant. (output) notifies an external device it has been granted the system bus. pulled high - note[1] note [3] l_fclk/ gpio[74] icocz lcd frame clock. (output) indicates the start of a new frame. also referred to as vsync. pulled high - note[1] note [3] l_lclk/ gpio[75] icocz lcd line clock. (output) indicates the start of a new line. also referred to as hsync. pulled high - note[1] note [3] l_pclk/ gpio[76] icocz lcd pixel clock. (output) clocks valid pixel data into the lcd line-shift buffer. pulled high - note[1] note [3] l_bias/ gpio[77] icocz ac bias drive. (output) notifies the panel to change the polarity for some passive lcd panel. for tft panels, this signal indicates valid pixel data. pulled high - note[1] note [3] full function uart pins ffrxd/ gpio[34] icocz full function uart receive. (input) mmc chip select 0. (output) chip select 0 for the mmc controller. pulled high - note[1] note [3] fftxd/ gpio[39] icocz full function uart transmit. (output) mmc chip select 1. (output) chip select 1 for the mmc controller. pulled high - note[1] note [3] ffcts/ gpio[35] icocz full function uart clear-to-send. (input) pulled high - note[1] note [3] ffdcd/ gpio[36] icocz full function uart data-carrier-detect. (input) pulled high - note[1] note [3] ffdsr/ gpio[37] icocz full function uart data-set-ready. (input) pulled high - note[1] note [3] table 3. pin and signal descriptions for the pxa255 processor (sheet 4 of 9) pin name type signal descriptions reset state sleep state
package information intel? pxa255 processor electrical, mechanical, and thermal specification 13 ffri/ gpio[38] icocz full function uart ring indicator. (input) pulled high - note[1] note [3] ffdtr/ gpio[40] icocz full function uart data-terminal-ready. (output) pulled high - note[1] note [3] ffrts/ gpio[41] icocz full function uart request-to-send. (output) pulled high - note[1] note [3] bluetooth uart pins btrxd/ gpio[42] icocz bluetooth uart receive. (input) pulled high - note[1] note [3] bttxd/ gpio[43] icocz bluetooth uart transmit. (output) pulled high - note[1] note [3] btcts/ gpio[44] icocz bluetooth uart clear-to-send. (input) pulled high - note[1] note [3] btrts/ gpio[45] icocz bluetooth uart request-to-send. (output) pulled high - note[1] note [3] standard uart and icp pins irrxd/ gpio[46] icocz irda receive signal. (input) receive pin for the fir function. standard uart receive. (input) pulled high - note[1] note [3] irtxd/ gpio[47] icocz irda transmit signal. (output) transmit pin for the standard uart, sir and fir functions. standard uart transmit. (output) pulled high - note[1] note [3] hardware uart pins hwrxd/ gpio[42/49] icocz hardware uart receive. (input) pulled high - note[1] note [3] hwtxd/ gpio[43/48] icocz hardware uart transmit. (output) pulled high - note[1] note [3] hwcts/ gpio[44/50] icocz hardware uart clear-to-send. (input) pulled high - note[1] note [3] hwrts/ gpio[45/51] icocz hardware uart data-terminal-ready. (output) pulled high - note[1] note [3] mmc controller pins mmcmd icocz multimedia card command. (bidirectional) hi-z hi-z mmdat icocz multimedia card data. (bidirectional) hi-z hi-z npce[2]/ gpio[53] icocz pcmcia card enable 2. (outputs) selects a pcmcia card. bit one enables the high byte lane and bit zero enables the low byte lane. mmc clock. (output) clock signal for the mmc controller. pulled high - note[1] note [5] l_dd[9]/ gpio[67] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 0. (output) chip select 0 for the mmc controller. pulled high - note[1] note [3] table 3. pin and signal descriptions for the pxa255 processor (sheet 5 of 9) pin name type signal descriptions reset state sleep state
package information 14 intel? pxa255 processor electrical, mechanical, and thermal specification l_dd[10]/ gpio[68] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc chip select 1. (output) chip select 1 for the mmc controller. pulled high - note[1] note [3] l_dd[11]/ gpio[69] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. mmc clock. (output) clock for the mmc controller. pulled high - note[1] note [3] ffrxd/ gpio[34] icocz full function uart receive. (input) mmc chip select 0. (output) chip select 0 for the mmc controller. pulled high - note[1] note [3] fftxd/ gpio[39] icocz full function uart transmit. (output) mmc chip select 1. (output) chip select 1 for the mmc controller. pulled high - note[1] note [3] mmcclk/ gp[6] icocz mmc clock. (output) clock signal for the mmc controller. pulled high - note[1] note [3] mmccs0/ gp[8] icocz mmc chip select 0. (output) chip select 0 for the mmc controller. pulled high - note[1] note [3] mmccs1/ gp[9] icocz mmc chip select 1. (output) chip select 1 for the mmc controller. pulled high - note[1] note [3] ssp pins sspsclk/ gpio[23] icocz synchronous serial port clock. (output) pulled high - note[1] note [3] sspsfrm/ gpio[24] icocz synchronous serial port frame. (output) pulled high - note[1] note [3] ssptxd/ gpio[25] icocz synchronous serial port transmit. (output) pulled high - note[1] note [3] ssprxd/ gpio[26] icocz synchronous serial port receive. (input) pulled high - note[1] note [3] sspextclk/ gpio[27] icocz synchronous serial port external clock. (input) pulled high - note[1] note [3] nssp pins nsspsclk/ gpio[81] icocz network synchronous serial port clock. (output/input) pulled high - note[1] note [3] nsspsfrm/ gpio[82] icocz network synchronous serial port frame. (output/input) pulled high - note[1] note [3] nssptxd/ gpio[83] icocz network synchronous serial port transmit/recieve. (output/input) pulled high - note[1] note [3] nssprxd/ gpio[84] icocz network synchronous serial port transmit/receive. (output/input) pulled high - note[1] note [3] usb client pins usb_p iaoaz usb client positive. (bidirectional) hi-z hi-z usb_n iaoaz usb client negative pin. (bidirectional) hi-z hi-z table 3. pin and signal descriptions for the pxa255 processor (sheet 6 of 9) pin name type signal descriptions reset state sleep state
package information intel? pxa255 processor electrical, mechanical, and thermal specification 15 ac97 controller and i 2 s controller pins bitclk/ gpio[28] icocz ac97 audio port bit clock. (input) ac97 clock is generated by codec 0 and fed into the pxa255 processor processor and codec 1. ac97 aaudio port bit clock. (output) ac97 clock is generated by the pxa255 processor. i 2 s bit clock. (input) i 2 s clock is generated externally and fed into pxa255 processor. i 2 s bit clock. (output) i 2 s clock is generated by the pxa255 processor. pulled high - note[1] note [3] sdata_in0/ gpio[29] icocz ac97 audio port data in. (input) input line for codec 0. i 2 s data in. (input) input line for the i 2 s controller. pulled high - note[1] note [3] sdata_in1/ gpio[32] icocz ac97 audio port data in. (input) input line for codec 1. i 2 s system clock. (output) system clock from i 2 s controller. pulled high - note[1] note [3] sdata_out/ gpio[30] icocz ac97 audio port data out. (output) output from the pxa255 processor to codecs 0 and 1. i 2 s data out. (output) output line for the i 2 s controller. pulled high - note[1] note [3] sync/ gpio[31] icocz ac97 audio port sync signal. (output) frame sync signal for the ac97 controller. i 2 s sync. (output) frame sync signal for the i 2 s controller. pulled high - note[1] note [3] nacreset oc ac97 audio port reset signal. (output) driven low driven low i 2 c controller pins scl icocz i 2 c clock. (bidirectional) hi-z hi-z sda icocz i 2 c data. (bidirectional). hi-z hi-z pwm pins pwm[1:0]/ gpio[17:16] icocz pulse width modulation channels 0 and 1. (outputs) pulled high - note[1] note [3] dma pins dreq[1:0]/ gpio[19:20] icocz dma request. (input) notifies the dma controller that an external device requires a dma transaction. dreq[1] is gpio[19]. dreq[0] is gpio[20]. pulled high - note[1] note [3] gpio pins gpio[1:0] icocz general purpose i/o. wakeup sources on both rising and falling edges on nreset. pulled high - note[1] note [3] gpio[14:2] icocz general purpose i/o. more wakeup sources for sleep mode. pulled high - note[1] note [3] gpio[22:21] icocz general purpose i/o. additional general purpose i/o pins. pulled high - note[1] note [3] crystal and clock pins pxtal oa 3.6864 mhz crystal input. no external caps are required. note [2] note [2] pextal ia 3.6864 mhz crystal output. no external caps are required. note [2] note [2] txtal oa 32 khz crystal input. no external caps are required. note [2] note [2] table 3. pin and signal descriptions for the pxa255 processor (sheet 7 of 9) pin name type signal descriptions reset state sleep state
package information 16 intel? pxa255 processor electrical, mechanical, and thermal specification textal ia 32 khz crystal output. no external caps are required. note [2] note [2] l_dd[12]/ gpio[70] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. rtc clock. (output) real time clock 1 hz tick. pulled high - note[1] note [3] l_dd[13]/ gpio[71] icocz lcd display data. (output) transfers the pixel information from the lcd controller to the external lcd panel. 3.6864 mhz clock. (output) output from 3.6864 mhz oscillator. pulled high - note[1] note [3] l_dd[14]/ gpio[72] icocz lcd display data. (output) transfers pixel information from the lcd controller to the external lcd panel. 32 khz clock. (output) output from the 32 khz oscillator. pulled high - note[1] note [3] 48mhz/gp[7] icocz 48 mhz clock. (output) peripheral clock output derived from the pll. note: this clock is only generated when the usb unit clock enable is set. pulled high - note[1] note [3] rtcclk/ gp[10] icocz real time clock. (output) 1 hz output derived from the 32 khz or 3.6864 mhz output. pulled high - note[1] note [3] 3.6mhz/gp[11] icocz 3.6864 mhz clock. (output) output from 3.6864 mhz oscillator. pulled high - note[1] note [3] 32khz/gp[12] icocz 32 khz clock. (output) output from the 32 khz oscillator. pulled high - note[1] note [3] miscellaneous pins boot_sel [2:0] ic boot select pins. (input) indicates type of boot device. input input pwr_en oc power enable for the power supply. (output) when negated, it signals the power supply to remove power to the core because the system is entering sleep mode. driven high driven low while entering sleep mode. driven high when sleep exit sequence begins. nbatt_fault ic main battery fault. (input) signals that main battery is low or removed. assertion causes pxa255 processor processor to enter sleep mode or force an imprecise data exception, which cannot be masked. pxa255 processor will not recognize a wake-up event while this signal is asserted. minimum assertion time for nbatt_fault is 1 ms. input input nvdd_fault ic vdd fault. (input) signals that the main power source is going out of regulation. nvdd_fault causes the pxa255 processor to enter sleep mode or force an imprecise data exception, which cannot be masked. nvdd_fault is ignored after a wake-up event until the power supply timer completes (approximately 10 ms). minimum assertion time for nvdd_fault is 1 ms. input input nreset ic hard reset. (input) level -sensitive input used to start the processor from a known address. assertion terminates the current instruction abnormally and causes a reset. when nreset is driven high, the processor starts execution from address 0. nreset must remain low until the power supply is stable and the internal 3.6864 mhz oscillator has stabilized. input input. driving low during sleep will cause normal reset sequence and exit from sleep mode. table 3. pin and signal descriptions for the pxa255 processor (sheet 8 of 9) pin name type signal descriptions reset state sleep state
package information intel? pxa255 processor electrical, mechanical, and thermal specification 17 nreset_out oc reset out. (output) asserted when nreset is asserted and deasserts after nreset is de-asserted but before the first instruction fetch. nreset_out is also asserted for ?soft? reset events: sleep, watchdog reset, or gpio reset. driven low during any reset sequence - driven high prior to first fetch. driven low jtag and test pins ntrst ic jtag test interface reset. resets the jtag/debug port. if jtag/debug is used, drive ntrst from low to high either before or at the same time as nreset. if jtag is not used, ntrst must be either tied to nreset or tied low. input input tdi ic jtag test data input. (input) data from the jtag controller is sent to the pxa255 processor using this pin. this pin has an internal pull-up resistor. input input tdo ocz jtag test data output. (output) data from the pxa255 processor is returned to the jtag controller using this pin. hi-z hi-z tms ic jtag test mode select. (input) selects the test mode required from the jtag controller. this pin has an internal pull-up resistor. input input tck ic jtag test clock. (input) clock for all transfers on the jtag test interface. input input test ic test mode. (input) reserved. must be grounded. input input testclk ic test clock. (input) reserved. must be grounded. input input power and ground pins vcc sup positive supply for internal logic. must be connected to the low voltage supply on the pcb. powered note [6] vss sup ground supply for internal logic. must be connected to the common ground plane on the pcb. grounded grounded pll_vcc sup positive supply for plls and oscillators. must be connected to the common low voltage supply. powered note [6] pll_vss sup ground supply for the pll. must be connected to common ground plane on the pcb. grounded grounded vccq sup positive supply for all cmos i/o except memory bus and pcmcia pins. must be connected to the common 3.3v supply on the pcb. powered note [7] vssq sup ground supply for all cmos i/o except memory bus and pcmcia pins. must be connected to the common ground plane on the pcb. grounded grounded vccn sup positive supply for memory bus and pcmcia pins. must be connected to the co mmon 3.3v or 2.5v supply on the pcb. powered note [7] vssn sup ground supply for memory bus and pcmcia pins. must be connected to the common ground plane on the pcb. grounded grounded table 3. pin and signal descriptions for the pxa255 processor (sheet 9 of 9) pin name type signal descriptions reset state sleep state
package information 18 intel? pxa255 processor electrical, mechanical, and thermal specification table 4. pin description notes note description [1] gpio reset operation: configured as gpio inputs by defau lt after any reset. the input buffers for these pins are disabled to prevent current drain and the pins are pulled high with 10k to 60k internal resistors. the input paths must be enabled and the pullups turned off by clearing the read-disable-hold (rdh) bit described in section 3.5.7, ?power manager sleep status register (pssr)? on page 3-27 in the intel? pxa255 processor developers manual . even though sleep mode sets the rdh bit, the pull-up resistors are not re-enabled by sleep mode. [2] crystal oscillator pins: these pins connect the external crystals to the on-chip oscillators. refer to section 3.3.1, ?32.768 khz oscillator? on page 3-4 in the intel? pxa255 processor developers manual and section 3.3.2, ?3.6864 mhz oscillator? on page 3-4 of the intel? pxa255 processor developers manual for details on sleep- mode operation. [3] gpio sleep operation: the state of these pins is determined by the corresponding pgsrn during the transition into sleep mode. see section 3.5.9, ?power manager gpio sleep state registers (pgsr0, pgsr1, pgsr2)? and section 4.1.3.2, ?gpio pin direction registers (gpdr0, gpdr1, gpdr2)? on page 4-8 in the intel? pxa255 processor developers manual . if selected as an input, this pin does not drive during sleep. if selected as an output, the value contained in the sleep-state regi ster is driven out onto the pin and held there while the pxa255 processor is in sleep mode. gpios configured as inputs after exiting sleep mode cannot be used until pssr[rdh] is cleared. [4] static memory control pins: during sleep mode, these pins can be programmed to either drive the value in the sleep-state register or be placed in hi-z. to select the hi-z state, software must set the fs bit in the power- manager general-configuration register. if pcfr[fs] is not set, then during the transition to sleep these pins function as described in [3], above. for nwe, noe, and ncs[0], if pcfr[fs] is not set, they are driven high by the memory controller before entering sleep. if pc fr[fs] is set, these pi ns are placed in hi-z. [5] pcmcia control pins: during sleep mode: can be programmed either to drive the value in the sleep-state register or be placed in hi-z. to select the hi-z state, software must set pcfr[fp]. if it is not set, then during the transition to sleep these pins function as described in [3], above. [6] during sleep, this supply may be driven low. this supply must never be high impedance. [7] remains powered in sleep mode.
package information intel? pxa255 processor electrical, mechanical, and thermal specification 19 figure 2. pxa255 processor
package information 20 intel? pxa255 processor electrical, mechanical, and thermal specification table 5. pxa255 processor 256-lead 17x17mm mbga pinout ? ballpad no. order (sheet 1 of 3) ball # signal ball # signal ball # signal a1 vccn c10 vccq f3 nsdcas a2 l_dd[13]/gpio[71] c11 vssq f4 vccn a3 l_dd[12]/gpio[70] c12 usb_p f5 sdclk[1] a4 l_dd[11]/gpio[69] c13 vccq f6 vssq a5 l_dd[9]/gpio[67] c14 vssq f7 gpio[10] a6 l_dd[7]/gpio[65] c15 irtxd/gpio[47] f8 ffrts/gpio[41] a7 gpio[11] c16 vss f9 sspsclk/gpio[23] a8 l_bias/gpio[77] d1 sdclk[2] f10 ffdtr/gpio[40] a9 ssprxd/gpio[26] d2 sdclk[0] f11 vcc a10 sdata_out/gpio[30] d3 rdnwr f12 gpio[9] a11 sda d4 vccn f13 boot_sel[2] a12 ffdcd/gpio[36] d5 l_dd[10]/gpio[68] f14 gpio[8] a13 ffrxd/gpio[34] d6 l_dd[5]/gpio[63] f15 vssq a14 ffcts/gpio[35] d7 l_dd[1]/gpio[59] f16 nsspsclk/gpio[81] a15 btcts/gpio[44] d8 l_lclk/gpio[75] g1 ma[0] a16 sdata_in1/gpio[32] d9 ssptxd/gpio[25] g2 vssn b1 dqm[1] d10 nacreset g3 nsdcs[2] b2 dqm[2] d11 scl g4 nwe b3 l_dd[15]/gpio[73] d12 pwm[1]/gpio[17] g5 noe b4 gpio[14] d13 bttxd/gpio[43] g6 nsdcs[1] b5 gpio[13] d14 mmcmd g7 vcc b6 gpio[12] d15 vccq g8 vssq b7 l_dd[3]/gpio[61] d16 nssprxd/gpio[84] g9 vcc b8 l_pclk/gpio[76] e1 nsdras g10 vssq b9 sspextclk/gpio[27] e2 vssn g11 testclk b10 ffri/gpio[38] e3 sdcke[1] g12 test b11 ffdsr/gpio[37] e4 sdcke[0] g13 boot_sel[1] b12 usb_n e5 l_dd[6]/gpio[64] g14 vccq b13 btrxd/gpio[42] e6 l_dd[4]/gpio[62] g15 gpio[7] b14 btrts/gpio[45] e7 l_dd[[0]/gpio[58] g16 boot_sel[0] b15 irrxd/gpio[46] e8 l_fclk/gpio[74] h1 ma[2] b16 mmdat e9 sspsfrm/gpio[24] h2 ma[1] c1 rdy/gpio[18] e10 sdata_in0/gpio[29] h3 md[16] c2 vssn e11 sync/gpio[31] h4 vccn c3 l_dd[14]/gpio[72] e12 pwm[0]/gpio[16] h5 md[17] c4 vssq e13 fftxd/gpio[39] h6 ma[3]
package information intel? pxa255 processor electrical, mechanical, and thermal specification 21 c5 l_dd[8]/gpio[66] e14 vccq h7 vssq c6 vccq e15 nssptxd/gpio[83] h8 vss c7 l_dd[2]/gpio[60] e16 nsspsfrm/gpio[82] h9 vss c8 vssq f1 nsdcs[0] h10 vcc c9 bitclk/gpio[28] f2 nsdcs[3] h11 ntrst h12 tck l9 vcc p6 md[24] h13 tms l10 gpio[0] p7 md[26] h14 gpio[6] l11 pwr_en p8 md[27] h15 tdi l12 gpio[1] p9 ncs[2]/gpio[78] h16 tdo l13 gpio[2] p10 md[29] j1 ma[7] l14 vssq p11 md[12] j2 vssn l15 textal p12 md[31] j3 ma[6] l16 txtal p13 npoe/gpio[48] j4 md[18] m1 ma[14] p14 npce[1]/gpio[52] j5 ma[5] m2 md[21] p15 vssn j6 ma[4] m3 ma[15] p16 npsktsel/gpio[54] j7 vcc m4 vccn r1 ma[18] j8 vss m5 md[1] r2 vssn j9 vss m6 md[6] r3 ma[20] j10 vssq m7 md[7] r4 vssn j11 gpio[5] m8 dqm[0] r5 ma[22] j12 gpio[4] m9 md[8] r6 vssn j13 nreset m10 md[15] r7 md[25] j14 vssq m11 vccq r8 vssn j15 pll_vcc m12 gpio[22] r9 md[10] j16 pll_vss m13 npreg/gpio[55] r10 vssn k1 ma[8] m14 vccn r11 md[30] k2 ma[9] m15 vssn r12 vssn k3 md[19] m16 niois16/gpio[57] r13 ncs[4]/gpio[80] k4 vccn n1 md[22] r14 vssn k5 ma[10] n2 vssn r15 npiow/gpio[51] k6 ma[11] n3 ma[16] r16 npce[2]/gpio[53] k7 vssq n4 md[0] t1 vss k8 vcc n5 vccn t2 vccn k9 vssq n6 md[4] t3 md[23] k10 vcc n7 vccn t4 ma[21] k11 nreset_out n8 ncs[0] t5 ma[24] table 5. pxa255 processor 256-lead 17x17mm mbga pinout ? ballpad no. order (sheet 2 of 3) ball # signal ball # signal ball # signal
electrical specifications 22 intel? pxa255 processor electrical, mechanical, and thermal specification 3.2 package power ratings 4.0 electrical specifications 4.1 absolute maximum ratings this section provides the absolute maximum ratings for the processors. do not exceed these parameters or the part may be damaged permanently. operation at absolute maximum ratings is not guaranteed . k12 nbatt_fault n9 vccn t6 md[3] k13 nvdd_fault n10 md[13] t7 md[5] k14 gpio[3] n11 vccn t8 ncs[1]/gpio[15] k15 pxtal n12 dreq[0]/gpio[20] t9 ncs[3]/gpio[79] k16 pextal n13 vccn t10 md[9] l1 ma[12] n14 dreq[1]/gpio[19] t11 md[11] l2 vssn n15 gpio[21] t12 md[14] l3 ma[13] n16 npwait/gpio[56] t13 ncs[5]/gpio[33] l4 md[20] p1 ma[17] t14 npwe/gpio[49] l5 md[2] p2 ma[19] t15 npior/gpio[50] l6 vcc p3 vccn t16 vccn l7 dqm[3] p4 ma[25] l8 md[28] p5 ma[23] table 6. ja and maximum power ratings processor ja max power pxa255 33 c /w 1.4w table 5. pxa255 processor 256-lead 17x17mm mbga pinout ? ballpad no. order (sheet 3 of 3) ball # signal ball # signal ball # signal
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 23 4.2 power consumption specifications power consumption depends on the operating voltage, peripherals enabled, external switching activity, and external loading. specifying maximum power consumption requires all units to be run at their maximum performance, and at maximum voltage and loading conditions. the maximum power consumption of the pxa255 processor is calculated using these conditions: ? all peripheral units operating at maximum frequency and size configuration ? all i/o loads maximum (50 pf) ? core operating at worst-case power scenario (hit rates adjusted for worst power) ? all voltages at maximum of range. maximum range for the core voltage is set to maintain compatibility with the pxa250. ? maximum case temperature do not exceed the maximum package power rating or t case temperature. since few systems operate at maximum loading, performance, and voltage, a more optimal system design requires more typical power-consumption figures. these figures are important when considering battery size and optimizing regulator efficiency. typical systems operate with fewer modules active and at nominal voltage and load. the typical power consumption for the pxa255 processor is calculated using these conditions: ? ssp, stuart, usb, pwm, timer, i2s peripherals operating table 7. absolute maximum ratings symbol description min max units ts storage temperature -40 125 c vss_o offset voltage between any two vss pins (vss, vssq, vssn) -0.3 0.3 v vcc_o offset voltage between any of the following pins: vccq and vccn -0.3 0.3 v vcc_hv voltage applied to high voltage supplies (vccq, vccn) vss-0.3 vss+4.0 v vcc_lv voltage applied to low voltage supplies (vcc, pll_vcc) vss-0.3 vss+1.65 v vip voltage applied to non-supply pins except xtal pins vss-0.3 max of vccq+0.3, vss+4.0 v vip_x voltage applied to xtal pins (pxtal, pextal, txtal, textal) vss-0.3 max of vcc+0.3, vss+1.65 v vesd maximum esd stress voltage, human body model; any pin to any supply pin, either polarity, or any pin to all non- supply pins together, either polarity. three stresses maximum. 2000 v ieos maximum dc input current (electrical overstress) for any non-supply pin 5 ma
electrical specifications 24 intel? pxa255 processor electrical, mechanical, and thermal specification ? lcd enabled with 320x240x16-bit color ? mmc, ac97, btuart, ffuart, icp, i2c peripherals disabled ? i/o loads at nominal (35 pf for all pins) ? core operating at 98% instruction hit rate, 95% data hit rate, run mode ? all voltages at nominal values ? nominal case temperature table 8 contains power consumption numbers for the pxa255 processor. table 8. power consumption specifications for pxa255 processor (sheet 1 of 2) symbol description typical maximum units 400 mhz active mode, maximum: v cc =1.65v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.3v, v ccq /v ccn =3.3v, temp=room i ccc v cc current 245 800 ma i ccp v ccq and v ccn current 28 355 ma p total tot a l p o we r 411 2598 mw 300 mhz active mode, maximum: v cc =1.43v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.1v, v ccq /v ccn =3.3v, temp=room i ccc v cc current 185 570 ma i ccp v ccq and v ccn current 24 345 ma p total tot a l p o we r 283 2057 mw 200 mhz active mode, maximum: v cc =1.32v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.0v, v ccq /v ccn =3.3v, temp=room i ccc v cc current 115 340 ma i ccp v ccq and v ccn current 19 330 ma p total tot a l p o we r 178 1637 mw 400 mhz idle mode, maximum: v cc =1.65v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.3v, v ccq /v ccn =3.3v, temp=room i ccc v cc current 95 460 ma i ccp v ccq and v ccn current 9 50 ma p total tot a l p o we r 121 939 mw 300 mhz idle mode, maximum: v cc =1.43v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.1v, v ccq /v ccn =3.3v, temp=room i ccc v cc current 43 335 ma i ccp v ccq and v ccn current 9 50 ma p total tot a l p o we r 77 659 mw 200 mhz idle mode, maximum: v cc =1.32v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.0v, v ccq /v ccn =3.3v, temp=room i ccc v cc current 33 205 ma i ccp v ccq and v ccn current 9 50 ma p total tot a l p o we r 63 451 mw 33 mhz idle mode, maximum: v cc =1.32v, v ccq /v ccn =3.6v, temp=100 c typical: v cc =1.0v, v ccq /v ccn =3.3v, temp=room
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 25 4.3 operating conditions this section shows voltage, frequency, and temperature specifications for the processor for four different ranges (shown in table 9, ?voltage, temperature, and frequency electrical specifications? .) the temperature specification for each range is constant; the frequency range depends on the operation voltage. note: the parameters in table 9 are preliminary and subject to change. i ccc v cc current 15 70 ma i ccp v ccq and v ccn current 9 50 ma p total to ta l po w e r 45 272 mw sleep mode, maximum: v cc =0v, v ccq /v ccn =3.3v, temp=room i ccp v ccq and v ccn current 45 75 a fast sleep wakeup mode, maximum: v cc =1.0/1.1/1.3v, v ccq /v ccn =3.3v, temp=room i ccc v cc current - - ? i ccp v ccq and v ccn current - - - table 8. power consumption specifications for pxa255 processor (sheet 2 of 2) symbol description typical maximum units table 9. voltage, temperature, and frequency electrical specifications (sheet 1 of 2) symbol description min typical max units t case case temperature - extended temp -40 - 100 c t case case temperature - nominal temp 0 - 85 c vvss vss, vssn, vssq voltage -0.3 0 0.3 v vvccq vccq voltage 3.0 3.3 3.6 v vvccn vccn voltage 2.375 2.5/3.3 3.6 v low voltage range vvcc_l vcc, pll_vcc voltage, low range .95 1.00 1.155 v fturbo_l turbo mode frequency, low range 99.5 118 mhz fsdram_l external synchronous memory frequency, low range 50 99.5 mhz medium voltage range vvcc_m vcc, pll_vcc voltage, mid range .95 1.00 1.32 v fturbo_m turbo mode frequency, mid range 99.5 199.1 mhz fsdram_m external synchronous memory frequency, mid range 50 99.5 mhz high voltage range vvcc_h vcc, pll_vcc voltage, high range 1.045 1.1 1.43 v fturbo_h turbo mode frequency, high range 99.5 298.7 mhz fsdram_h external synchronous memory frequency, high range 50 99.5 mhz
electrical specifications 26 intel? pxa255 processor electrical, mechanical, and thermal specification 4.4 targeted dc specifications the dc characteristics for each pin include input-sense levels and output-drive levels and currents. these parameters can be used to determine maximum dc loading, and also to determine maximum transition times for a given load. table 10, ?standard input, output, and i/o pin dc operating conditions? shows the dc operating conditions for the high- and low-strength input, output, and i/o pins. all dc specification values are valid for the entire temperature range of the device. peak voltage range vvcc_p vcc, pll_vcc voltage, peak range 1.235 1.30 1.65 v fturbo_p turbo mode frequency, peak range 99.5 398.2 mhz fsdram_p external synchronous memory frequency, peak range 50 99.5 mhz table 9. voltage, temperature, and frequency electrical specifications (sheet 2 of 2) symbol description min typical max units table 10. standard input, output, and i/o pin dc operating conditions symbol description min typical max units input dc operating conditions vih input high voltage, all standard input and i/o pins 0.8*vccq vccq v vil input low voltage, all standard input and i/o pins vss 0.2*vccq v iin input leakage, all standard input and io pins 10 a output dc operating conditions voh output high voltage, all standard output and i/o pins vccq-0.1 vccq v vol output low voltage, all standard output and i/o pins vss vss+0.4 v ioh_h output high current, all standard, high- strength output and i/o pins (vo=voh) -10 ma ioh_l output high current, all standard, low- strength output and i/o pins (vo=voh) -3 ma iol_h output low current, all standard, high- strength output and i/o pins (vo=voh) 10 ma iol_l output low current, all standard, low- strength output and i/o pins (vo=voh) 3 ma
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 27 4.5 targeted ac specifications all the non-analog input, output, and i/o pins on the processor can be divided into one of two categories: 1. high strength input, output, and i/o pins: ? ncs[5:1] (gp 33, 80, 79, 78, 15 respectively), ncs[0] ? md[31:0], ma[25:0] ? dqm[3:0] ? noe, nwe, nsdras, nsdcas, nsdcs[3:0] ? sdclk[2:0], sdcke[1:0] ? rdnwr, rdy (gp[18]) ? npwe, npoe pins (gp[49:48]) ? mmclk (gp[53]), mmcmd, mmdat ? tdo ? nacreset 2. low strength input, output, and i/o pins - all remaining non-supply pins a pin?s ac characteristics include input and output capacitance, which determine loading for external drivers or other load analysis. the ac characteristics also include a de-rating factor, which indicates how much faster or slower the ac timings get with different loads. table 12, ?standard input, output, and i/o pin ac operating conditions? shows the ac operating conditions for the high- and low-strength input, output, and i/o pins. all ac specification values are valid for the entire temperature range of the device. table 11. standard input, output, i/o pin dc operating conditions for 2.5-v memory symbol description min typ max units input dc operating conditions vih input high voltage, all standard input and i/o pins 0.9*vccn vccn v vil input low voltage, all standard input and i/o pins vss 0.1*vccn v iin input leakage, all standard input and i/o pins -10ua output dc operating conditions voh output high voltage, all standard output and i/o pins vccn-0.3 vccn v vol output low voltage, all standard output and i/o pins vss vss+0.3 v
electrical specifications 28 intel? pxa255 processor electrical, mechanical, and thermal specification 4.6 oscillator electrical specifications the processor contains two oscillators, each for a specific crystal: a 32.768-khz oscillator and a 3.6864-mhz oscillator. when choosing a crystal, match the crystal parameters as closely as possible. 4.6.1 32.768-khz oscillator specifications the 32.768-khz oscillator is connected between the txtal (amplifier input) and textal (amplified output). table 13, ?32.768-khz oscillator specifications? shows the 32.768-khz specifications. table 12. standard input, output, and i/o pin ac operating conditions symbol description min typical max units cin input capacitance, all standard input and io pins 10 pf cout_h output capacitance, all standard high- strength output and io pins 25 1 50 1 pf tdf_h output de-rating, falling edge on all standard, high-strength output and i/o pins, from 50pf load. ns/pf tdr_h output de-rating, rising edge on all standard, high-strength output and i/o pins, from 50pf load. ns/pf note: 1 ac specifications guaranteed for loads in this range. all testing is done at 50pf table 13. 32.768-khz oscillator specifications symbol description min typical max units crystal specifications - typical is fox nc38 f xt crystal frequency, txtal/textal ? 32.768 ? khz esr equivalent series resistance, txtal/textal 6 ? 65 k ? p drive level ? ? 1 uw amplifier specifications vih_x input high voltage, txtal 0.8*vcc vcc v vil_x input low voltage, txtal vss 0.2*vcc v iin_xt input leakage, txtal 1 a cin_xt input capacitance, txtal/textal 18 25 pf ts_xt stabilization time 2 - 10 s board specifications rp_xt parasitic resistance, txtal/textal to any node 20 m ? cp_xt parasitic capacitance, txtal/textal, total 5 pf cop_xt parasitic shunt capacitance, txtal to textal 0.4 pf
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 29 to drive the 32.768-khz crystal pins from an external source ? drive the textal pin with a digital signal that has a low level near 0 volts and a high level near vcc. do not exceed vcc or go below vss by more than 100 mv. the minimum slew rate is 1 volt per 1 s. the maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 ma. ? float the txtal pin or drive it complementary to the textal pin, with the same voltage level, slew rate, and input current restrictions. 4.6.2 3.6864 mhz oscillator specifications the 3.6864-mhz oscillator is connected between the pxtal (amplifier input) and pextal (amplified output). table 14 shows the 3.6864-mhz specifications. to drive the 3.6864-mhz crystal pins from an external source ? drive the pextal pin with a digital signal with a low level near 0 volts and a high level near vcc. do not exceed vcc or go below vss by more than 100 mv. the minimum slew rate is 1 volt / 100 ns. the maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 ma. ? float the pxtal pin or drive it complementary to the pxtal pin, with the same voltage level, slew rate, and input current restrictions. if floated, some degree of noise susceptibility will be introduced in the system; therefore, it is not recommended. table 14. 3.6864-mhz oscillator specifications symbol description min typical max units crystal specifications - typical is fox hc49s f xp crystal frequency, pxtal/pextal ? 3.6864 ? mhz esr equivalent series resistance, pxtal/pextal 50 - 300 ? p drive level ? ? 100 uw amplifier specifications vih_x input high voltage, pxtal 0.8*vcc vcc v vil_x input low voltage, pxtal vss 0.2*vcc v iin_xp input leakage, pxtal 10 a cin_xp input capacitance, pxtal/pextal 40 50 pf ts_xp stabilization time 17.8 67.8 ms board specifications rp_xp parasitic resistance, pxtal/pextal to any node 20 m ? cp_xp parasitic capacitance, pxtal/pextal, total 5 pf cop_xp parasitic shunt capacitance, pxtal to pextal 0.4 pf
electrical specifications 30 intel? pxa255 processor electrical, mechanical, and thermal specification note: the minimum duty cycle for an external signal driven into pextal is 40/60. 4.7 reset and power ac timing specifications the processor asserts the nreset_out pin in one of several different modes: ? power on ? hardware reset ? watchdog reset ? gpio reset ? sleep mode the following sections provide the timing and specifications for the entry and exit of these modes. 4.7.1 power-on timing the external voltage regulator and other power-on devices must provide the processor with a specific sequence of power and resets to ensure proper operation. figure 3, ?power-on reset timing? on page 31 , shows this sequence and is detailed in table 15, ?power-on timing specifications? on page 31 . on the processor, it is important that the power supplies be powered up in a certain order to avoid high current situations. the required order is: 1. vccq 2. vccn 3. vcc and pll_vcc on the processor, it is important that the vccq power supply be powered up before or at the same time as the vccn power supply. the vcc and pll_vcc power supplies may be powered up anytime within the specification shown in figure 3 and table 15 .
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 31 note: if hardware reset is entered during sleep mode, follow the proper power-supply stabilization times indicated in figure 3 and nreset timing requirements indicated in table 15 . figure 3. power-on reset timing table 15. power-on timing specifications symbol description min typical max units tr_vccq vccq rise / stabilization time 0.01 ? 100 ms tr_vccn vccn rise / stabilization time 0.01 ? 100 ms tr_vcc vcc, pll_vcc rise / stabilization time 0.01 ? 10 ms td_vccn delay between vccq applied and vccn applied 0 ? ? ms td_vcc delay from vccn applied and vcc, pll_vcc applied -10 ? ? ms td_ntrst delay between vcc, pll_vcc stable and ntrst de-asserted 10 ? ? ms td_jtag delay between ntrst de-asserted and jtag pins active, with nreset asserted 0.03 ? ? ms td_nreset delay between vcc, pll_vcc stable and nreset de-asserted 10 ? ? ms td_out delay between nreset de-asserted and nreset_out de--asserted 18.1 ? 18.2 ms td_ncs0 delay between nreset_out deasserted and ncs0 asserted 400 ? 420 ns vccq, pwr_en vcc ntrst jtag pins nreset nreset_out t r_vccq t r_vcc t d_ntrst t d_jtag t d_nreset t d_out vccn t r_vccn t d_vcc t d_vccn notes: 1. nbatt_fault and nvdd_fault must be high before nreset_out is deasserted or the processor enters sleep mode. 2. the inclusion of pwr_en is for informational pur poses only to show its relationship to vccq. the use of pwr_en to bring up vccn or vcc at power-on reset is optional depending on the system?s power management requirements. vccn and vcc are not dependant on the pwr_en signal being asserted.
electrical specifications 32 intel? pxa255 processor electrical, mechanical, and thermal specification 4.7.2 hardware reset timing the timing sequences shown in hardware reset timing for hardware reset assumes stable power supplies at the assertion of nreset. if the power supplies are unstable, follow the timings indicated in section 4.7.1, ?power-on timing? on page 30 . 4.7.3 watchdog reset timing watchdog reset is an internally generated reset and therefore has no external pin dependencies. the nreset_out pin is the only indicator of watchdog reset, and it stays asserted for t dhw_out . refer to figure 4, ?hardware reset timing? on page 32 . 4.7.4 gpio reset timing gpio reset is generated externally, and the source is reconfigured as a standard gpio as soon as the reset propagates internally. the clocks module is not reset by gpio reset, so the timing varies based on the frequency of clock selected, and if the clocks and power manager is in the frequency change sequence when gpio reset is asserted (see section 4.6.1, ?32.768-khz oscillator specifications? on page 28 .) figure 5, ?gpio reset timing? on page 33 shows the possible timing of gpio reset. figure 4. hardware reset timing table 16. hardware reset timing specifications symbol description min typical max units tdhw_nreset minimum assertion time of nreset 0.001 ms tdhw_out_a delay betw een nreset asserted and nreset_out asserted 0 0.001 ms tdhw_out delay between nreset de-a sserted and nreset_out de-asserted 18.1 18.2 ms tdhw_ncs0 delay between nreset_out de-asserted and ncs0 asserted 400 ? 420 ns nreset nreset_out t dhw_nreset t dhw_out note: nba tt_fault and nvdd_f ault must be high before nreset is deasserted or the cotulla will enter sleep mode t dhw_out_a note: nbatt_fault and nvdd_fault must be high before nreset is de-asserted or the pxa255 processor enters sleep mode.
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 33 4.7.5 sleep mode timing sleep mode is asserted internally; and asserts the nreset_out and pwr_en signals. the sequence indicated in figure 6, ?sleep mode timing? on page 34 and detailed in figure 18, ?sleep mode timing specifications? on page 34 is the required timing parameters for sleep mode. figure 5. gpio reset timing table 17. gpio reset timing specifications symbol description min typical max units ta_gp[1] minimum assert time of gp[1] 1 in 3.6864mhz input clock cycles 4 cycles tdhw_out_a delay between gp[1] asserted and nreset_out asserted in 3.6864 mhz input clock cycles 3 8 cycles tdhw_out delay between nreset_out asserted and nreset_out de-asserted, run or turbo mode 2 1.28 6.5 s tdhw_out_f delay between nreset_out asserted and nreset_out de-asserted, during frequency change sequence 3 1.28 360 s tdhw_ncs0 delay between nreset_out de-asserted and ncs0 asserted 150.69 ? 390 ns notes: 1. gp[1] is not recognized as a reset source again un til configured to do so in software. software should check the state of gp[1] before configuring as a reset to ensure no spurious reset is generated. 2. time is 512*n processor clock cycles plus up to 4 cycles of the 3.6864-mhz input clock. 3. time during the frequency change sequence depends on the state of the pll lock detector at the assertion of gpio reset. the lock detector has a maximum time of 350s plus synchronization. gp[1] nreset_out t dhw_out t a_ gp [1 ] t dhw_out_a note: nbatt_fault and nvdd_fault must be high before nreset is deasserted or the application processor will enter sleep mode
electrical specifications 34 intel? pxa255 processor electrical, mechanical, and thermal specification figure 6. sleep mode timing table 18. sleep mode timing specifications symbol description min typical max units ta_gp[x} assert time of gpio wake-up source (x=[15:0]) 91.6 ? ? s td_pwr_f delay from nreset_out asserted to pwr_en de-asserted 61 ? 91.6 s td_pwr_r delay between gp[x] asserted to pwr_en asserted 30.5 ? 122.1 s tdsm_vcc delay between pwr_en asserted and vcc stable ? 10 ms td_fault delay between pwr_en asserted and nvdd_fault de-asserted ? 10 ms tdsm_out delay between pwr_en asserted and nreset_out de-asserted, opde set 28.0 ? 28.5 ms tdsm_out_f delay between pwr_en asserted and nreset_out de-asserted, fwake set ? ? 650 s tdsm_out_o delay between pwr_en asserted and nreset_out de-asserted, opde clear 10.35 ? 10.5 ms t dsm_ncs0 delay between nreset_out de-asserted and ncs0 asserted 180.84 ? 332 ns note: for the parameter t dsm_vcc , vcc refers to the vcc supply inter nal to the processor. the internal vcc regulator must be stable within the stated maximum for the processor to function correctly. factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of the internal regulator and must be taken into account when designing the system. gp[x] pwr_en vcc nvdd_fault nreset_out t dsm_out note: nba tt_fault must be high or cotulla will not exit sleep mode t a_ g p [ x] t d_pwr_r t d_pwr_f t d_f a ul t t dsm_vcc note: nbatt_fault must be high or the pxa255 processor will not exit sleep m ode.
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 35 4.8 memory bus and pcmcia ac specifications this section provides the timing information for these types of memory: ? sram / rom / flash / synchronous fast flash asynchronous writes ( table 19, ?sram / rom / flash / synchronous fast flash ac specifications? on page 35 ) ? variable latency i/o ( table 20, ?variable latency i/o interface ac specifications? on page 35 ) ? card interface (pcmcia or compact flash) ( table 21, ?card interface (pcmcia or compact flash) ac specifications? on page 36 ) ? synchronous memories ( table 22, ?synchronous memory interface ac specifications 1? on page 36 ) table 19. sram / rom / flash / synchronous fast flash ac specifications symbol description memclks tromas ma(25:0) setup to ncs, noe, nsdcas (as nadv) asserted 1 tromah ma(25:0) hold after ncs, noe, nsdcas (as nadv) de- asserted 1 tromasw ma(25:0) setup to nwe asserted 3 tromahw ma(25:0) hold after nwe de-asserted 1 tromces ncs setup to nwe asserted 2 tromceh ncs hold after nwe de-asserted 1 tromds md(31:0), dqm(3:0) write data setup to nwe asserted 1 tromdswh md(31:0), dqm(3:0) write data setup to nwe de-asserted 2 tromdh md(31:0), dqm(3:0) write data hold after nwe de-asserted 1 tromnwe nwe high time between beats of write data 2 table 20. variable latency i/o interface ac specifications symbol description memclks tvlioas ma(25:0) setubp to ncs asserted 1 tvlioasrw ma(25:0) setup to noe or npwe asserted 1 tvlioah ma(25:0) hold after noe or npwe de-asserted 1 tvlioces ncs setup to noe or npwe asserted 2 tvlioceh ncs hold after noe or npwe de-asserted 1 tvliodsw md(31:0), dqm(3:0) write data setup to npwe asserted 1 tvliodswh md(31:0), dqm(3:0) write data setup to npwe de- asserted 2 tvliodhw md(31:0), dqm(3:0) hold after npwe de-asserted 1 tvliodhr md(31:0) read data hold after noe de-asserted 0 tvliordyh rdy hold after noe, npwe de-asserted 0 tvlionpwe npwe, noe high time between beats of write or read data 2
electrical specifications 36 intel? pxa255 processor electrical, mechanical, and thermal specification table 21. card interface (pcmcia or compact flash) ac specifications symbol description memclks tcardas ma(25:0), npreg, psktsel, npce setup to npwe, npoe, npiow, or npior asserted 2 tcardah ma(25:0), npreg, psktsel, npce hold after npwe, npoe, npiow, or npior de-asserted 2 tcardds md(31:0) setup to npwe, npoe, npiow, or npior asserted 2 tcarddh md(31:0) hold after npwe, npoe, npiow, or npior de-asserted 2 tcardcmd npwe, npoe, npiow, or npior command assertion 2 note: these numbers are minimums. they can be much longer based on the programmable card interface timing registers. table 22. synchronous memory interface ac specifications 1 symbol description min max units, notes sdram / smrom / sdram-timing synchronous flash (synchronous) tsynclk sdclk period 10 20 ns, 2 tsyncmd nsdcas, nsdras, nwe, nsdcs assert time 1 sdclk tsynrcd nsdras to nsdcas assert time 1 sdclk tsyncas nsdcas to nsdcas assert time 2 sdclk tsynsdos ma(25:0), md(31:0), dqm(3:0), nsdcs(3:0), nsdras, nsdcas, nwe, noe, sdcke(1:0), rdnwr output setup time to sdclk(2:0) rise 3.8 ns, 3 tsynsdoh ma(25:0), md(31:0), dqm(3:0), nsdcs(3:0), nsdras, nsdcas, nwe, noe, sdcke(1:0), rdnwr output hold time from sdclk(2:0) rise 3.6 ns, 3 tsynsdis md(31:0) read data input setup time from sdclk(2:0) rise 0.5 ns tsyndih md(31:0) read data input hold time from sdclk(2:0) rise 1.5 ns fast flash (synchronous reads only) tffclk sdclk period 15 20 ns, 4 tffas ma(25:0) setup to nsdcas (as nadv) asserted 0.5 sdclk tffces ncs setup to nsdcas (as nadv) asserted 0.5 sdclk tffadv nsdcas (as nadv) pulse width 1 sdclk tffos nsdcas (as nadv) de-assertion to noe assertion 3 sdclk tffceh noe deassertion to ncs de-assertion 4 sdclk notes: 1. these numbers are for a maximum 99.5 mhz memclk and 99.5 mhz output sdclk. 2. sdclk for sdram, smrom, and sdram-timing synchronous flash can be at the slowest, divide-by-2 of the 99.5 mhz memclk. it can be 99.5 mhz at the fastest. 3. this number represents 1/2 sdclk period. 4. sdclk for fast flash can be at the slowest, divide -by-2 of the 99.5 mhz memclk. it can be divide-by-2 of the 132.7 mhz memclk at its fastest.
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 37 4.9 peripheral module ac specifications this section describes the ac specifications for the lcd and ssp peripheral units. 4.9.1 lcd module ac timing figure 7 describes the lcd timing parameters. the lcd pin timing specifications are referenced to the pixel clock (l_pclk). values for the parameters are given in table 23 . 4.9.2 ssp module ac timing figure 8, ?ssp ac timing definitions? on page 38 describes the ssp timing parameters. the ssp pin timing specifications are referenced to sclk_c. values for the parameters are given in table 24, ?ssp ac timing specifications? on page 38 . figure 7. lcd ac timing definitions table 23. lcd ac timing specifications symbol description min max units notes tpclkdv tpclkdv l_pclk rise/fall to l_ldd<7:0> driven valid 03.5ns1 tpclklv l_pclk fall to l_lclk driven valid -0.5 2.0 ns 2 tpclkfv l_pclk fall to l_fclk driven valid -0.5 2.0 ns 2 tpclkbv l_pclk rise to l_bias driven valid 5.524 12 ns 2 notes: 1. program the lcd data pins to be driven on either the rising or falling edge of the pixel clock (l_pclk). 2. these lcd signals can, at times, transition when l_pcl k is not clocking (between frames). at this time, they are clocked with the internal version of the pixel clock before it is driven out onto the l_pclk pin. a4775-01 l_ldd[7:0] (rise) l_ldd[7:0] (fall) l_pclk l_lclk l_bias l_fclk t pclkdv t pclklv t pclkfv t pclkbv t pclkdv
electrical specifications 38 intel? pxa255 processor electrical, mechanical, and thermal specification 4.9.3 boundary scan test signal timings table 25, ?boundary scan test signal timing? shows the boundary scan test signal timing. figure 8. ssp ac timing definitions table 24. ssp ac timing specifications symbol description min max units notes tsf m v sclk_c rise to sfrm_c driven valid 21 ns trxds rxd_c valid to sclk_c fall (input setup) 11 ns trxdh sclk_c fall to rxd_c invalid (input hold) 0 ns tsf m v sclk_c rise to txd_c valid 22 ns a4774-01 sclk_c sfrm_c txd_c rxd_c t sfmv t sfmv t rxds t rxdh table 25. boundary scan test signal timing (sheet 1 of 2) symbol parameter min max units notes tbsf tck frequency 0.0 33.33 mhz tbsch tck high time 15.0 ns measured at 1.5 v tbscl tck low time 15.0 ns measured at 1.5 v tbscr tck rise time 5.0 ns 0.8 v to 2.0 v tbscf tck fall time 5.0 ns 2.0 v to 0.8 v tbsis1 input setup to tck tdi, tms 4.0 ns tbsih1 input hold from tck tdi, tms 6.0 ns tbsis2 input setup to tck ntrst 25.0 ns tbsih2 input hold from tck ntrst 3.0 ns tbsov1 tdo valid delay 1.5 6.9 ns relative to falling edge of tck tof1 tdo float delay 1.1 5.4 ns relative to falling edge of tck tov12 all outputs (non-test) valid delay 1.5 6.9 ns relative to falling edge of tck
electrical specifications intel? pxa255 processor electrical, mechanical, and thermal specification 39 4.10 ac test conditions the ac specifications in section 4.5, ?targeted ac specifications? on page 27 are tested with a 50 pf load indicated in figure 9 . tof2 all outputs (non-test) float delay 1.1 5.4 ns relative to falling edge of tck tis10 input setup to tck all inputs (non-test) 4.0 ns tih8 input hold from tck all inputs (non-test) 6.0 ns table 25. boundary scan test signal timing (sheet 2 of 2) symbol parameter min max units notes figure 9. ac test load output ball c l c l = 50pf

▲Up To Search▲

Price & Availability of GDPXA255

	To Download GDPXA255 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .